Visualizer 3: SIMD Micro-Kernels

Sliding Stencils & Vector Lanes

How does a $3 \times 3$ image spatial filter vectorize across CPU vector registers? Watch SIMD vector lanes calculate 4 or 8 adjacent output pixels simultaneously with reflection padding.

Center Pixel: (X=4, Y=4) SIMD: 4 Lanes (NEON/WASM)

Filter Settings

Spatial Operator

Vector Architecture

Filter Scan Speed 1.0×

SIMD Register Lanes

Parallel outputs computed in single instruction:

Lane 0
P(x+0)

Lane 1
P(x+1)

Lane 2
P(x+2)

Lane 3
P(x+3)

Border Padding Mode:

Reflection: (border - d)