Visualizer 2: Cache Hierarchy
Tiled GEMM & Cache Hierarchy
Why does naive matrix multiplication run at 5% of peak hardware capacity while cache-tiled GEMM achieves 90%? Watch cache blocks move between RAM, L1 Cache, and SIMD Vector Registers in real time.
Execution Controls
Tile Block Size (B)
4 × 4
Animation Speed
1.0×
Hardware Diagnostics
L1 Data Cache Hit Rate
96.8%
Memory Bus Saturation
18.4 GB/s
Effective Compute Rate
72.96 GFLOPS